Switched current delta-sigma modulator

ABSTRACT

A noise-limiting, switched current delta-sigma modulator for use in, for example, an oversampling analog-to-digital converter. The modulator includes a first integrator having a relatively large bias current and one or more second integrators having relatively small bias currents. The modulator according to the present invention reduces power consumption and chip area.

FIELD OF THE INVENTION

The present invention generally relates to switched-current delta-sigmamodulators, such as are used in oversampling analog-to-digital (A/D)converters. More specifically, the present invention provides adelta-sigma modulator which offers reduced power consumption and chiparea.

BACKGROUND OF THE INVENTION

Traditionally, analog circuits have been used extensively in signalprocessing applications. Recently, however, digital signal processingcircuits have been used in conjunction with analog processing circuits.It is relatively inexpensive to fabricate high density digital circuits,but is relatively expensive to integrate analog circuit components.Accordingly, in many signal processing applications, the source anddestination circuits are analog circuits, while much of the signalprocessing is performed by digital circuits. Therefore,analog-to-digital (A/D) and digital-to-analog (D/A) converters areimportant signal processing components.

Traditional Nyquist A/D converters typically require high accuracyanalog components and high performance anti-aliasing filters. Because ofthis requirement, oversampling A/D converters are often preferredbecause they do not require high accuracy analog components or highperformance anti-aliasing filters. Oversampling A/D converters insteadrequire high performance digital circuits, which are relativelyinexpensive. An oversampling A/D converter usually consists of adelta-sigma modulator (analog circuits) and a digital decimation filter.To realize delta-sigma modulators, the switched-capacitor (SC) techniqueis typically employed. However, the SC technique requires linearcapacitors that are not practical in a digital CMOS baseline fabricationprocess. To create linear capacitors, extra process steps are needed inthe digital CMOS baseline fabrication process, increasing the cost. Torealize delta-sigma modulators in a pure digital CMOS process, aswitched-current (SI) technique is desirable in which currents aresignal carriers. An extensive treatment of SI delta-sigma modulators isprovided in "Oversampling A/D Converters and Current-Mode Techniques" byNianxiong Tan (1994), and related publications. Circuit noise (e.g.,thermal noise) limits dynamic range more than the quantization noise. InSI circuits, the dynamic range can be increased without reducing speedby increasing the bias current, thereby increasing the highest inputcurrent. The above publication reveals that for every doubling of biascurrents, the dynamic range of any SI circuit can be increased by 3 dBwithout speed penalty. For high-order delta-sigma modulators, thethermal noise rather than the quantization noise limits the performance.The dynamic range of modulators is limited by the dynamic range of theconstituent SI circuits. However, increasing the bias currents for allthe SI circuits in a delta-sigma modulator to achieve high dynamic rangeis very power consuming, and results in inefficient use of chip area.

SUMMARY OF THE INVENTION

The present invention overcomes the above-described problems, andprovides other advantages, by providing for a switched-current (SI)delta-sigma modulator for use in an oversampling analog-to-digital (A/D)converter. The invention includes, in two exemplary embodiments, a firstintegrator having a relatively large bias current, and therefore arelatively large dynamic range. The exemplary modulators further includeone or more second integrators, having a relatively small bias current.The modulators according to the present invention offer reduced powerconsumption and chip area. The power consumption and chip area savingsincrease as the number of integrators (i.e., the order of the modulator)increases.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present invention can be obtainedby reading the following Detailed Description of the PreferredEmbodiments in conjunction with the accompanying drawings, in which likereference indicia indicate like elements, and in which:

FIG. 1 is a block diagram of a noise-limiting switched currentdelta-sigma modulator according to an exemplary embodiment of thepresent invention; and

FIG. 2 is a block diagram of a fourth-order delta-sigma modulatoraccording to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A noise-limiting switched current delta-sigma modulator according to anexemplary embodiment of the present invention is shown in FIG. 1. Themodulator 10 shown is a second order modulator, and includes first andsecond combiners 12 and 18, first and second integrators 14 and 20,first and third amplifiers 16 and 22, and a 1-bit current quantizer 24.The modulator further includes first and second digital-to-analogconverters 26 and 28, and a second amplifier 30.

The first combiner 12 receives an input current signal and combines theinput current signal with the signal output by D/A converter 26, whichis an analog version of the digital output signal generated by currentquantizer 24. Specifically, the first combiner 12 subtracts the analogversion of the digital output signal from the input current signal toproduce a first combined signal. First integrator 14 integrates thefirst combined signal and supplies a first integrated signal to firstamplifier 16, which amplifies the first integrated signal by a firstscaling factor a. First integrator 14 is biased with a first biascurrent, which is relatively large compared to the bias current of thesecond integrator. According to one exemplary embodiment, the first biascurrent is approximately four times larger than the bias current of thesecond integrator. However, this ratio is dependent upon the selectionof the scaling factors for the first and second amplifiers 16 and 30, aswill be discussed in more detail below.

Second combiner 18 combines the first amplified signal output by firstamplifier 16 with the signal output by second amplifier 30, which is ananalog version of the digital output signal generated by currentquantizer 24 amplified by a second scaling factor b in second amplifier30. Specifically, second combiner 18 subtracts the amplified analogversion of the digital output signal from the first amplified signal togenerate a second combined signal. Second integrator 20 integrates thesecond combined signal and supplies a second integrated signal to thirdamplifier 22, which amplifies the second integrated signal by a thirdscaling factor c. Second integrator 20 is biased with a second biascurrent, which is smaller than the first bias current, as describedabove. Finally, current quantizer 24 quantizes the second amplifiedsignal to generate the digital output signal, which is fed back to firstand second combiners 12 and 18 via D/A converters 26 and 28,respectively. Preferably, current quantizer 24 is a single-bit quantizerand first and second D/A converters 26 and 28 are single-bit converters.

First and second integrators 14 and 20 can have transfer functions ofapproximately z⁻¹ /(1-z⁻¹), or another suitable transfer function.

In a delta-sigma modulator, only the noise at the first integrator inputlimits the dynamic range, since noise introduced at other nodes issuppressed at low frequencies by the noise reduction feedback loopformed by D/A converters 26 and 28, and second amplifier 30 in themodulator. The third scaling factor c introduced immediately precedingthe single bit current quantizer 24 by third amplifier 22 can be anyarbitrary positive factor without having any influence on thequantization, since the quantizer senses only current direction. It willbe appreciated that the scaling factor can be distributed within themodulator. When the input current is scaled down, the followingmodulator stage can have a smaller bias current.

Therefore, in a noise-limiting SI delta-sigma modulator, a large biascurrent in the first integrator provides a large dynamic range; in thefollowing integrators smaller bias currents can be used if the signal isproperly scaled by suitable connected scaling elements such asamplifiers 22 and 30.

In traditional switched-capacitor (SC) realizations, the scaling factorsa, b, and c are chosen such that the signal swing in both integratorsare equal. In conventional switched-current (SI) realizations, the sameguideline is used, though scalings in SC and SI differ. In anoise-limiting modulator, a large bias current in both integratorsimproves dynamic range (for example, 3 dB increase in range is possiblefor each doubling of the bias currents). In a delta-sigma modulator(e.g., as shown in FIGS. 1 and 2), as long as the first integrator has asufficient dynamic range, the modulator can deliver a high dynamic rangeregardless of the second integrator bias current, since noise present inthe second integrator experiences noise shaping due to the feedbackloop. Therefore, current can be aggressively scaled before being fed tothe second integrator. Due to second scaling factor b, the signal swingin the second integrator is much smaller than in the first integratorand therefore a smaller bias current is sufficient. By scaling thesignal swings within each integrator, power and chip area can be saved.

The third scaling factor c does not influence the signal transfer andnoise shaping functions. The relationship between a and b is determinedby the noise shaping function (b=2a), but the values can be chosen toscale the signal (current) swing in the second integrator. If a=0.5 andb=1, the signal swings in both integrator are the same (this is thegeneral practice for SI delta-sigma modulators). If a=1/8 and b=1/4, thesignal swing in the second integrator is four times smaller than in thefirst integrator. Obviously, the bias current in the second integratorcan be four times smaller.

The principle described above is general and can be applied to any SIdelta-sigma modulator. The higher order the modulator is, the moreefficient the method is. In order to achieve a high dynamic range, thefirst integrator occupies the most chip area and dissipates the mostpower; the remaining integrators can be designed with very small chiparea and power consumption. The use of a large bias current in the firstintegrator improves the dynamic range since the modulator's dynamicrange is limited by the dynamic range in the first integrator. Theinfluence of the quantization noise can usually be made very small inhigh-order modulators. To illustrate the point, an example of afourth-order delta-sigma modulator is shown in FIG. 2.

The fourth-order delta-sigma modulator of FIG. 2 includes twosecond-order delta-sigma modulators 10a and 10b, each of which issubstantially similar to the second-order delta-sigma modulator 10 shownin FIG. 1. In the embodiment shown in FIG. 2, the second modulator 10bincludes an additional amplifier 27b between first D/A converter 26b andfirst combiner 12b. The second integrated signal generated by secondintegrator 20a of first modulator 10a is amplified by the second scalingfactor by third amplifier 22a, and this amplified connecting signal issupplied as the analog input signal to the first combiner 12b of secondmodulator 10b. The connecting scaling factor, according to an exemplaryembodiment, is approximately 1/2.

The first digital output signal from quantizer 24a of first modulator10a is supplied to an output delay element 32, and the delay elementoutput signal is supplied to first and second output combiners 34 and36. The second digital output signal from quantizer 24b of secondmodulator 10b is amplified by an output scaling factor in outputamplifier 38. The amplified second digital output signal is supplied tofirst output combiner 34, which subtracts the delay element outputsignal from the amplified second digital output signal to generate afirst combined output signal. The first combined output signal fromfirst combiner 34 is differentiated in an output differentiator 40, andthe differentiated signal is supplied to second output combiner 36.Second output combiner 36 subtracts the signal output by outputdifferentiator 40 from the delay element output signal from delayelement 32 to generate a digital output signal. It will be appreciatedthat the principles of the present invention can be implemented in thisor any other suitable fourth-order delta-sigma modulator arrangement.

According to an exemplary embodiment, the transfer functions of theintegrators 14a, 14b, 20a, and 20b can be approximately z⁻¹ /(1-z⁻¹),the transfer function of the output delay element 32 can beapproximately z⁻², and the transfer function of the outputdifferentiator 40 can be approximately (1-z⁻¹)². Further, according tothe same embodiment, the scaling factor of first amplifier 16a isapproximately 1/8, the scaling factor of amplifiers 27, 30a, and 30b isapproximately 1/4, the scaling factor of amplifiers 22a and 16b isapproximately 1/2, and the scaling factor of output amplifier 38 isapproximately 4.

In conventional modulators, all the integrators typically have the samesignal swing. In the modulator of the present invention, the signalswing in the first integrator is e.g., four times larger than that inall the other integrators. The scaling does not change the signaltransfer or noise shaping function. However, the bias currents in theintegrators except for the first one can be smaller and powerconsumption and chip area can be reduced.

As described above, the present invention provides improved SIdelta-sigma modulators, by fully utilizing the facts that signal swingsin SI circuits are independent of the supply voltage and that byreducing the signal swing, the power consumption and chip area can bereduced. To achieve a high dynamic range in SI delta-sigma modulators, alarge signal swing in the first integrator provides a high dynamicrange. The dynamic range in the first integrator is the fundamentallimitation of the dynamic range of the SI delta-sigma modulator,regardless of the circuit configurations and system structures. Themodulators according to the invention maintain a large signal swing inthe first integrator and reduce signal swing in all other integratorsthrough scaling. By doing so, a modulator having high dynamic range withlow power and small chip area can be achieved.

While the foregoing description has included many details andspecificities, it is to be understood that these are for illustrativepurposes only, and are not to be construed as limitation of theinvention. Numerous modifications to the above-described embodimentswill be readily apparent to those of ordinary skill in the art which areencompassed by the spirit and scope of the present invention, as definedby the following claims and their legal equivalents.

What is claimed is:
 1. A delta-sigma modulator, comprising:a firstcombiner for generating a first combined signal by combining an analoginput current signal with an analog version of a digital output signal;a first integrator for integrating the first combined signal, the firstintegrator having a first bias current and a first signal swing; a firstamplifier for amplifying the first integrated signal by a first scalingfactor; a second amplifier for amplifying the analog version of thedigital output signal by a second scaling factor greater than the firstscaling factor; a second combiner for generating a second combinedsignal by combining the first amplified signal with the second amplifiedsignal; a second integrator for integrating the second combined signal,the second integrator having a second bias current smaller than thefirst bias current and a second signal swing which is less than aboutone-half the first signal swing; a third amplifier for amplifying thesecond integrated signal by a third scaling factor greater than thefirst scaling factor; and a current quantizer for quantizing the thirdamplified signal to generate the digital output signal.
 2. The modulatorof claim 1, wherein the first and second integrators have a transferfunction of approximately z⁻¹ /(1-z⁻¹).
 3. The modulator of claim 1,wherein the third scaling factor is approximately twice the firstscaling factor.
 4. The modulator of claim 3, wherein the third scalingfactor is approximately 1/4 and the first scaling factor isapproximately 1/8.
 5. The modulator of claim 1, further comprising adigital filter for filtering the digital output signal.
 6. The modulatorof claim 1, wherein the current quantizer is a single bit quantizer. 7.The modulator of claim 1, further comprising at least onedigital-to-analog converter for generating the analog version of thedigital output signal.
 8. The modulator of claim 7, wherein the at leastone digital-to-analog converter is a single bit digital-to-analogconverter.
 9. The modulator of claim 1, wherein the first combinersubtracts the analog version of the digital output signal from theanalog input signal and the second combiner subtracts the amplifiedanalog version of the digital output signal from the first amplifiedsignal.
 10. An analog to digital converter for converting an analoginput signal into a digital output signal, comprising:two or moredelta-sigma modulators, each delta-sigma modulator including a firstintegrator biased with a first bias current and one or more secondintegrators biased with one or more second bias currents, each secondbias current being less than about one-half the first bias current,wherein a first delta-sigma modulator includes a first amplifier forscaling a first integrator output signal by a first scaling factor, andthe converter further includes a plurality of additional amplifiers forscaling signals by at least approximately twice the first scalingfactor; a current quantizer for quantizing an integrated analog signaloutput by one of the one or more second integrators to generate thedigital output signal; and a noise reduction feedback loop for combiningthe digital output signal with the analog input signal and with anoutput signal from the first integrator.
 11. The analog to digitalconverter of claim 10, further comprising a digital decimation filter.12. The analog to digital converter of claim 10, wherein the first biascurrent is approximately four times as large as the one or more secondbias currents.
 13. The analog to digital converter of claim 10, whereinat least one of the additional amplifiers scales an output signal by ascaling factor which is approximately 32 times the first scaling factor.14. The analog to digital converter of claim 13, wherein the noisereduction feedback loop includes at least one digital to analogconverter for generating an analog version of the digital output signaland at least one feedback amplifier for scaling the analog version ofthe digital output signal by a feedback scaling factor.
 15. The analogto digital converter of claim 14, wherein the feedback scaling factor isapproximately twice the first scaling factor.
 16. The analog to digitalconverter of claim 10, wherein the first integrator and the one or moresecond integrators have a transfer function of approximately z⁻¹/(1-z⁻¹).
 17. The analog to digital converter of claim 10, wherein thefirst integrator is larger than the one or more second integrators. 18.A method for modulating/converting an analog input signal to a digitaloutput signal, comprising the steps of:combining the analog input signaland an analog version of the digital output signal to generate a firstcombined signal; integrating the first combined signal using anintegrator having a first bias current; amplifying the first integratedsignal by a first scaling factor; combining the first amplified signalwith a second amplified signal generated by amplifying the analogversion of the digital output signal by a second scaling factor togenerate a second combined signal; integrating the second combinedsignal using an integrator having second bias current smaller than thefirst bias current; amplifying the second integrated signal by a secondscaling factor greater than the first scaling factor; and quantizing theamplified second integrated signal to generate the digital outputsignal.